modelsim
Suntiamorntut E. Wannarat
[ Home | Research | Paper | Personal | Hardware Design Knowledge|]

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Rank : Lecturer
Status : Full-Time
Length of Service : Since August 1, 1999 - present
Experience

1 April 1998 - 30 June 1999	Researcher at Embedded System Lab, Computer Engineering Dept. KMITL.
1 April 1998 - 2000	Master.Eng(com) at Chulalongkron University
1 August 1999 - Present	Lecturer, Computer Engineering Dept. Prince of Songkla University
1 January 2002 - Present	Studying Ph.D. at University of Manchester, "Low-Power Asynchronous Digital Signal Processor"

Field of Specialization

Design and Verification Microprocessor Using VHDL on FPGA
Testing and Verification
Asynchronous Design
Low-Power Circuit Design

Link to Computer System Laboratory

Course

240-323 : Operating System
240-334 : Computer System Design
240-463(2/1999): Digital Communication Topic in System on a chip(SOC),and IC Design	:Introdution :What's core? How can I build on System using core?
	:CPLD lab
	:ABEL language
240-451 : VLSI Design
240-530 : Digital System Architecture
240-532 : Advanced Computer Architecture
Report nectec 6 months
spartan4k package for web_pack4.2
synthesis tool to generate EDIF
license for synthesis tool
how to install synthesis tool

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Computer Engineering Department, Prince of Songkla University
Tel.+66-74-287362 Fax. +66-74-212895
contact me